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Modify the Code of a pipelined RISC CPU in VHDL


The goal of part 1 of this project is to modify the code of part1.vhdl such that it handles the following instructions with no hazards: lw, sw, add, sub, or, addi, sll, srl, cmpl and nop This is a 5 part project, but I am only interested in getting the solutions to part1 and part2a. This shouldn't be too difficult for someone more familiar with vhdl, however it may take some time to read through the links given below to get a full understanding of what is required. For that reason, I am willing to pay $75 for the solution to part1, and $50 for the solution to part2a. part1.chk and part2a.chk are the expected outputs of part1.vhdl and part2a.vhdl respectively. bshift.vhdl and add32.vhdl are simply helper files that part1.vhdl will likely use. part1.abs and part2a.abs contain the memory for parts 1 and 2a (Not sure if these will be useful or not). I'm also not sure if and are useful. I'm pretty sure this project can be completed without even looking at these files. More detailed instructions are given in the following link: (*Not a CMPE Major) Additional help for part1 is given in the following link: Note that the areas of the code that need to modified within part1.vhdl are marked with the consecutive characters, ???. Thus, simply search '???' in the part1.vhdl file to see what work needs to be done. Schematics can be found by searching through the links above. No makefile given, so it might be best to compile and run it manually as shown in the first link. Attachments Tags


pipelined RISC CPU in VHDL


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part 1 & (46 K) Download

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