Find Us On: Facebook Twitter Rss Feed Blog
Need To Register? Sign Up Login

Simulate Cache Assignment

cero
cero 


See the following link for method and sample: http://www.csee.umbc.edu/~squire/cs411_l19.html Given the following sequences of word addresses, in decimal, 1, 4, 2, 7, 21, 4, 27, 3, 5, 24, 28, 19, 57, 1, 27, 3, 11 (no modification needed, just convert to binary 1 is 000001, 56 is 111000, etc, these are memory addresses) 1) Simulate an 8 word cache with one word per block, direct mapped. a) For each address, list the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. 2) Simulate a 16 word cache with four words per block, direct mapped. a) For each address, list the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. See attached image for formats. Attachments Tags Clarifications

Answers

Mr.

felo
felo 



1 Attachments
Screenshots
Purchase Answer