The goal of this project is to modify certain components of a pipelined RISC CPU as described in the links below.
Full project description in the following link:
This is a continuation of the 5-part project assignment from the following link:
The solutions to Part1 and Part2a are attached, along with other helper files.
I am looking for the solutions to part2b, part3a, and part3b.
part2b.chk, part3a.chk, and part3b.chk are the expected outputs of part2b.vhdl, part3a.vhdl, and part3b.vhdl, respectively.
The following link may help with part2b:
Hints that may or may not help with part3a:
It may take some reading to fully understand what is required, but I don't think this will be too difficult for someone more familiar with vhdl. Please message me if you have any questions.
$40 for part2b, $70 for part3a, and $40 for part3b for a total of $150.Attachments